An autoalignment method for realising a bipolar planar heterojunction transistor is known from the European Patent Application EP 0 322 960. In this application, the method comprises first the realisation of the two base contacts of the transistor on the upper surface of the device. These contacts are subsequently encapsulated and provided with spacers. The distance between the outer edges of the spacers defines the dimension of the emitter contact in the opening formed by the spacers between the base contacts. The lateral dimension of the spacers defines also the distance which separates each of the base contacts from the emitter contact.
According to this known method, however, the base and collector emitter layers form a superimposed semiconductor layer structure, while all the electrode contacts are realised on the upper surface of the device. This method therefore comprises manufacturing stages by localized implantation of a kind suitable for connecting the electrode contacts to the respective electrode layers.
Furthermore, the localized implantations turn out to be costly at present since they are difficult to carry out with precision; it is preferred not to use these techniques for the realisation of it is preferred not to use these techniques for the realisation of integrated circuits in great numbers. Under these circumstances, the problem arises of how to provide the contacts directly on the relevant layers by the simplest possible method, while at the same time the electrodes are made to be as close to one another as possible in order to obtain satisfactory devices which occupy the smallest possible surface area on the integrated circuit. In fact, if the emitter and base contacts are far apart from one another, parasitic elements will appear during operation which diminish the performance of the transistor, as is known to those skilled in the art.